1. Technical Field
The present disclosure relates to an electronic device, and more particularly to a delay cell and a digitally controlled oscillator.
2. Description of Related Art
A common digital phase-locked loop includes a phase frequency detector (PFD), a controller, a digitally controlled oscillator and a divider, wherein the digitally controlled oscillator utilizes a propagation path of a delay cell thereof and an inverter cell to form a feedback path, thereby creating an oscillation frequency.
A conventional delay cell may utilize signal delay characteristics of an inverter, an AND gate or a hysteresis element, to create the required delay time and the required oscillation frequency through a series-connection of multi-stage internal cells. When a wide frequency adjustment range is required, the number of series-connection stages of the internal cells in the delay cell has to be increased, so as to obtain various signal outputs with different delay times.
However, in a case that the multi-stage internal cells are connected in series (such as, series-connected inverters), the delay cell may occupy considerable power consumption in the digital phase-locked loop, which is unfavorable to actual applications. Therefore, the delay cell still has the aforementioned problems of power consumption and delay times to be overcome.